Transistors and Rectifiers Utilizing Hybrid Electrodes and Methods of Fabricating the Same
Systems methods and apparatus described herein are associated with devices including hybrid electrodes. A heterostructure semiconductor transistor can include a III-N-type semiconductor heterostructure including a barrier layer overlying an active layer and a hybrid electrode region including a hybrid drain electrode region. Further a heterostructure semiconductor rectifier can include a III-N-type semiconductor heterostructure and a hybrid electrode region including a hybrid cathode electrode region. Furthermore the hybrid electrode region of the transistor and rectifier can include permanently trapped charge located under a Schottky contact of the hybrid electrode region.
Countries or Regions:
US
Invention Code:
IP.PA.00435
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okt@ust.hk
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Category:
TAP - Microelectronics
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